1. Field of the Invention
The present invention generally relates to electronic systems having multiple levels in a memory hierarchy. More specifically, the present invention relates to addressing of redundant words in a register file.
2. Description of the Related Art
Modern electronic data processing systems (computer systems) typically have memory hierarchies. Memory hierarchies are dictated by economic and performance considerations. Memory hierarchies are made up of a plurality of groups of storage. Very fast storage, usually called “Level 1” cache is placed near a processor in the data processing system. A computer system typically has a level 1 instruction cache that holds instructions, and a level 1 data cache that holds data. “Level 2” cache, having capacity to store more data, but requiring longer to access is the next level of the memory hierarchy. Some computer systems have a “Level 3” cache having more storage than the level 2 cache but requiring even more time to access.
Computer systems also have register files, typically made up of groups of latches, that are used for “scratchpad” storage, and are directly addressed by instructions executed by the processor.
Many instructions contain logical addresses of words in a register file. “Words” in a register file are also called “registers” in the register file. A typical register file contains 32 8-byte (64-bit) words. Some earlier computer systems typically used 4-byte, 2-byte, or even 1-byte words in their register files. Some computer systems have register files having more than 32 words, some have fewer than 32 words. As described above, register files provide “scratchpad” storage for data or addresses used by the processor. Typically, an instruction may reference more than one word in the register file. For example, an instruction may specify that two words in the register file should be added, with the results stored in a third word in the register file. To accomplish this, the instruction contains an opcode (operational code) for “add”, and further contain the five-bit (for the exemplary 32 word register file) logical addresses for the two words to be added, and the five-bit logical address of the word to which the sum will be stored.
Register files are read and/or written during execution of most instructions. The high-speed nature of the register files and the frequent use of the register files make them tend to be “hot spots”, that is, they dissipate more power per unit area than much of the rest of the chip and are therefore at a higher temperature. Higher temperatures tend to accelerate defects, making register files prone to developing failures. The repetitive nature of register files (a repetition of bits “horizontally” for words, with a number (e.g., 32) words arranged “vertically”) allows for inclusion of a small number of redundant words. That is, a 32-word register file may physically have 33, 34, or more words, with one, two, or more words used as “spares” in case a defect introduced in manufacturing causes one or more of the 32 words (i.e., words 0–31) relied upon by the computer system to be faulty. In addition, the “spares” can be switched in if an error occurs during operation, although the computer system may have to backtrack and re-execute some instructions, or perhaps even have to re-start the task. Previously, addresses of identified faulty words were stored in an address compare unit and—when actually accessing the register file—compared with an address being used to fetch or store data in the register file. If the address being used to fetch or store data were the same as a stored faulty word, a first word line which activated all bits in the addressed word was held inactive, and a second word line was activated to access the redundant word. This was done during the actual fetch or store, which is typically a critical delay path that determines the frequency at which the processor would operate.
FIG. 1 illustrates a prior art example of such a conventional register file addressing scheme, accommodating a 32 word register file 17 (each word is also commonly known as a register in the register file). For simplicity, register file 17 includes a single port 19 through which data is read from or written into the register file. A register file addressing portion, generally designated as 10, of a computer system (not shown) comprises an instruction 11, fetched from a storage (not shown), typically an L1 cache. Instruction 11 contains a five bit register address which is coupled to a decode unit 13 by address bus 12. For simplicity, instruction 11 is shown to have only one register address; typically, instructions have more than one register address contained in the instruction. Decode 13 decodes the five bit address and activates one of 32 word lines in word line bus 14. Address bus 12 is also coupled to address compare 15, which compares (at the same time that decode 13 is decoding the address) the five bit address with one or more addresses that are known to address faulty words. Faulty words are identified during manufacturing tests of the semiconductor chip, during power on testing when the computer system is powered on, or during self diagnostics upon an error being detected during operation. For example, in the IBM Iseries computer system, a service processor is capable of responding to many error signals and diagnosing faults that resulted in the error signals. If the present five bit address matches an address of a faulty word, address compare 15 must immediately signal decode 13, before decode 13 can activate any of the 32 word lines, causing decode 13 to inhibit activating the one of 32 word lines corresponding to the address. Address compare 15, in addition, activates a redundant word line 16, which causes the contents of redundant word 18 to be accessed on register file port 19. Using this technique, redundant word 18 will always be used instead of the faulty word. The need to do an address compare in address compare 15 in time to inhibit decode 13 from activating one of 32 word lines is typically a cycle limiting path that limits the operating frequency of the computer system.
Therefore, a need exists to provide method and apparatus that allow a redundant word line in a register file to be accessed (fetched or stored) without having to compare, during the register file access, the address of word to be accessed to one or more faulty word addresses, and, respondent to an equal compare, suppressing access to the word in the logical address and accessing a redundant word.